As semiconductor technologies evolve, three dimensional (3D) integrated circuits (ICs) emerge as an effective alternative to further reduce the physical size of a semiconductor chip. One form of 3D IC is a chip-on-wafer-on-substrate (CoWoS) package. In a CoWoS package, a variety of chips comprising active circuits are first attached to an interposer wafer using micro-bumps (μbumps) to form a chip-on-wafer (CoW) structure. The variety of chips may be interconnected using through silicon vias (TSVs) in the interposer wafer. The CoW structure may then be attached to a substrate to form the completed CoWoS package. Typically, a CoWoS package allows for higher yield, higher connection densities, smaller form factors, and increased cost-effectiveness. A CoWoS package also allows for improved connections between the chip and the interposer wafer compared to other 3D IC packages (e.g., packages wherein the interposer wafer is first attached to the substrate before the variety of chips are attached).
As part of the CoW formation process, the number of μbumps used to connect the chip to the interposer wafer may number in the tens of thousands. A bad connection in any one of these μbumps may cause the entire packaged device to fail. Therefore, testing the interconnection quality of the CoW structure is an important aspect of the CoWoS packaging process. Currently, two types of CoW connection testing methods may be used: physical examination (e.g., a sampling of chips are x-rayed and examined manually) or product chip probing (CP).
Physical examination CoW testing may be unreliable and time-consuming. For example, a given wafer may include a hundred or more chips, and there may be twenty-five or more wafers in a lot. Furthermore, it may take a human twelve minutes or more to inspect a chip for bad connections. It is physically unrealistic to examine every chip in a lot; therefore, only a sampling of chips are examined (e.g., as few as five chips/wafer and one wafer/lot may be randomly sampled and examined). This low sampling rate restriction results in unreliable testing results, but sampling rates are not easily increased due to the time-consuming nature of the testing process. The unreliable nature of physical examination CoW testing may also be exacerbated by human error and limitations in the type of detectable connection failures (e.g., only bridged connections are readily visible, but other connection failures, such as voids, may still be present).
Product CP CoW testing involves functionally testing the electrical connections between the chip and the wafer. While this type of testing is less time consuming and more reliable than physical examination, product CP testing is inherently costly due to its chip-specific nature. That is, chip testing designs and testing probes are specific to a particular chip layout. Active circuits in a chip must be rerouted to peripheral regions of the interposer wafer to provide access for a testing probe to perform functional tests. This rerouting pattern is dependent on the circuit layout of a chip; therefore product CP testing creates an added cost for each chip and does not allow for standardized testing procedures.